Optimization and Implementation of DRAM-Based Interleavers for Free-Space Optical Communication Beyond 100 Gbit/s

Optical transmission links from low earth orbit (LEO) satellites to earth require interleaving to ensure reliable data transmission. With data rate requirements beyond 100 Gbit/s and channel coherence times in the millisecond range, the capacity of on-chip memory (SRAM) is insufficient to store the symbols of one full interleaving window, and external memory (DRAM) must be used instead. However, with DRAM, bandwidth utilization depends heavily on the access pattern. In the present application case of the right triangle interleaver, a two-dimensional array in the shape of an isosceles triangle is accessed both row-wise and column-wise. When this array is mapped to linear memory addresses in either row-major or columnmajor order, the bandwidth utilization for one of the two access directions is far below the theoretical maximum. This limits the overall throughput of the interleaver. We present an optimized mapping solution that is tailored to the internal DRAM architecture and minimizes the factors that restrict bandwidth utilization in both access directions simultaneously. Furthermore, this mapping solution can be applied to other problem instances involving alternating row- and column-wise accesses, including the more commonly used block interleaver. On the demonstrator platform, the AMD Alveo U280 accelerator card, the worst-case bandwidth utilization across both access directions is increased by 2.45 × for the DDR4 DRAM and 1.38 × for the HBM2 DRAM, while the overhead in FPGA resources is negligible. The complete interleaver design is then implemented on the platform, achieving a maximum data rate of 131.1 Gbit/s with the optimized mapping.