Reliability and Maintainability Evaluation of MVDC submodule Test Evaluation System by Fault-tree Analysis and Critical Maintenance Time Estimation | Zendy

Jae-Hun Cha | Zendy; Sang-Hyeok Lee | Zendy; Sung-Geun Song | Zendy; Feel-soon Kang | Zendy

Open Access

Reliability and Maintainability Evaluation of MVDC submodule Test Evaluation System by Fault-tree Analysis and Critical Maintenance Time Estimation

Author(s) -

Jae-Hun Cha,

Sang-Hyeok Lee,

Sung-Geun Song,

Feel-soon Kang

Publication year - 2025

Publication title -

ieee access

Language(s) - English

Resource type - Magazines

SCImago Journal Rank - 0.587

H-Index - 127

eISSN - 2169-3536

DOI - 10.1109/access.2025.3620283

Subject(s) - aerospace , bioengineering , communication, networking and broadcast technologies , components, circuits, devices and systems , computing and processing , engineered materials, dielectrics and plasmas , engineering profession , fields, waves and electromagnetics , general topics for engineers , geoscience , nuclear engineering , photonics and electrooptics , power, energy and industry applications , robotics and control systems , signal processing and analysis , transportation

This paper proposes a new RAM analysis method to evaluate a submodule test system’s Reliability, Availability, and Maintainability for MVDC in the early design stage. To reflect the risk according to the operating characteristics of the so-called Dual-mode test circuit (DTC) combined with the half-bridge submodule, the Mean Time to Failure (MTTF) and failure rate are derived using Fault-Tree Analysis (FTA). Considering the characteristics of the early design stage, where maintenance information is insufficient, the allowable limit of the essential maintenance time is inferred by applying the standardized test method and Operating Characteristic (OC) curve step by step. Finally, the minimum MTTF value to achieve the target availability is determined. The proposed RAM analysis method can provide a valuable guideline for evaluating a system’s Reliability, Availability, and Maintainability (RAM) in the early design stage.

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