Diagnostic Test Compaction of Functional Test Sequences
Author(s) -
Irith Pomeranz
Publication year - 2025
Publication title -
ieee access
Language(s) - English
Resource type - Magazines
SCImago Journal Rank - 0.587
H-Index - 127
eISSN - 2169-3536
DOI - 10.1109/access.2025.3618719
Subject(s) - aerospace , bioengineering , communication, networking and broadcast technologies , components, circuits, devices and systems , computing and processing , engineered materials, dielectrics and plasmas , engineering profession , fields, waves and electromagnetics , general topics for engineers , geoscience , nuclear engineering , photonics and electrooptics , power, energy and industry applications , robotics and control systems , signal processing and analysis , transportation
Functional test sequences are applied to detect defects that escape scan-based tests. The application of a functional test sequence requires a large number of clock cycles. Therefore, test compaction is applied to reduce the number of clock cycles without losing fault coverage. When a functional test sequence is used for logic diagnosis, it is important to ensure that test compaction does not eliminate useful diagnostic information. This article addresses this problem for the first time by describing a new test compaction procedure for functional test sequences. The ability of a sequence to support logic diagnosis is assessed by performing diagnostic fault simulation. To limit the computational effort, the test compaction procedure incorporates a dynamically changing parameter that limits the number of times diagnostic fault simulation is carried out during compaction. Experimental results for benchmark circuits demonstrate the effectiveness of the procedure, and the use of observation points.
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