Reinforcement Guided Genetic Algorithm for Application Mapping in Network-on-Chip Architectures: Towards Transparent and Efficient MPSoC Scheduling
Author(s) -
Ahmed Abbas Jasim Al-Hchaimi,
Mahmood A. Al-Shareeda,
Ahmad Taher Azar,
Walid El-Shafai
Publication year - 2025
Publication title -
ieee access
Language(s) - English
Resource type - Magazines
SCImago Journal Rank - 0.587
H-Index - 127
eISSN - 2169-3536
DOI - 10.1109/access.2025.3616179
Subject(s) - aerospace , bioengineering , communication, networking and broadcast technologies , components, circuits, devices and systems , computing and processing , engineered materials, dielectrics and plasmas , engineering profession , fields, waves and electromagnetics , general topics for engineers , geoscience , nuclear engineering , photonics and electrooptics , power, energy and industry applications , robotics and control systems , signal processing and analysis , transportation
In this paper, we present a novel hybrid application mapping framework that integrates Genetic Algorithm (GA) with Reinforcement Learning (RL) to optimize task allocation in 2D Network-on-Chip based Multiprocessor System-on-Chip (NoC-based MPSoC) architectures. The goal is to reduce overall communication costs and improve runtime efficiency during the task-to-core mapping process. The RL agent is embedded within the GA loop to dynamically steer selection, crossover, and mutation operations using real-time feedback on mapping quality. Our methodology is evaluated on both real applications (e.g., PIP, MPEG, VOPD) and synthetic TGFF workloads across NoC mesh sizes from 3x3 to 12x11. Experimental results demonstrate that GA+RL consistently outperforms the baseline GA. For instance, in the TGFF-G5 benchmark (80 cores), the GA+RL approach achieved a minimum communication cost of 116.354, compared to 244.645 with original GA, representing over 52% improvement. Across all trials, GA+RL also showed lower standard deviations and earlier convergence generations. To improve interpretability, we incorporate Explainable AI (XAI) techniques using SHapley Additive exPlanations (SHAP) to analyze feature contributions. Results reveal that average communication hops and total bandwidth are key factors influencing mapping efficiency. The GA+RL model demonstrates greater transparency and consistency, aiding design-time decisions. This work has direct implications for industrial platforms, including Kalray MPPA-256 (autonomous vehicles), Intel SCC (cloud/HPC), Adapteva Epiphany (IoT Edges), and Tilera TILE-Gx (Cybersecurity), where efficient and adaptive application mapping is critical. Aligned with UN SDG 2 (Zero Hunger), the framework also supports real-time scheduling in agriculture IoT systems, enabling energy-efficient deployment of smart technologies to enhance food production and sustainability.
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