Modeling, Analysis, and Comparison of Voltage and Charge Sampling Techniques in Sub-Sampling PLL Design

This paper compares two different architectures for implementing a sub-sampling phase-locked loop (SS-PLL). First, a time-domain model is used to analyze the noise contributions of the sampling mechanisms: voltage sampling (VS) and charge sampling (CS). Then, based on the obtained noise results, the performance of complete SS-PLL systems is evaluated using a phase-domain model. This approach applies to PLLs utilized as frequency synthesizers with large divide ratios (e.g., 64 to 512) as well as to SS-PLLs operating without a divider in their loop. Although the CS technique can theoretically enhance the Signal-to-Noise Ratio (SNR) by 3 dB compared to VS, the proposed phase-domain model highlights that, within typical power budgets ranging from 1 to 20 mW, a VS-PLL achieves a lower level of integrated jitter than a CS-PLL. This is due to the intrinsic noise of the charge sampling phase detector (CSPD) that, unlike in the VS-PLL, cannot be suppressed and therefore becomes the dominant in-band noise source.