New Generalized Multilevel Inverter Based on Developed H-Bridge with Reduced Circuit Component

Multilevel inverters have attracted much attention in recent years due to advantages such as reduced circuit component and simplicity of structure. Existing multilevel inverter topologies are usually associated with challenges such as reducing circuit component, etc. In this paper, two structures are presented, the first topology (topology I) is symmetric, and the second topology (topology II) is an improved topology I that can be implemented both symmetrically and asymmetrically. The basic topology I has a significant reduction in the number of switches compared to similar topologies. In addition, the basic topology I has low conduction losses compared to similar structures at the same voltage level due to the low number of ON-state switches. Topology I uses an H-bridge that has 4 high-stress switches, while topology II uses a developed H-bridge that only requires 2 high-stress switches. Topology II produces high voltage levels with high output power quality in the asymmetric mode. For topology I, phase-shift pulse width modulation (PWM) control is used, and for topology II, nearest level modulation (NLM) control is used. The efficiency of topology I with the values of losses and switch temperatures is also presented for each switch separately. A comparison is made with similar structures in terms of the number of switches and the number of drivers. The comparison results show that at equal levels, the proposed structures require fewer components. To verify the performance of the proposed design, the proposed topologies I and II are investigated from a hardware perspective. A laboratory implementation is used to evaluate the performance of the proposed configuration under steady-state and dynamic conditions.