A Programmable Active Recharge Circuit for SPAD in 110-nm BSI CMOS

This paper presents a programmable active recharge (AR) circuit optimized for a single-photon avalanche diode (SPAD) fabricated in a 110-nm BSI CMOS process. The SPAD employs a p-well and deep n-well junction. A retrograde p-substrate guard-ring, which is located at the junction edges, suppresses the premature breakdown of the SPAD. An NMOS recharge transistor is connected to the SPAD anode and is driven by an active recharge signal (Φ AR ), which is generated by the AR circuit. The AR circuit consists of an NMOS recharge transistor (M AR ), a current-starved inverter chain, and an AND gate, which detects the SPAD pulse and recharges the SPAD for the consecutive photon detection. By controlling the bias of the inverter chain, the delay and pulse width of Φ AR (DEL and WID) can be externally controlled. To optimize the timing of the AR circuit, an afterpulsing probability (APP) is characterized using inter-avalanche histogramming technique. The APP is measured at 0.1% with an interval range of 20 μs. When adjusting the delay of Φ AR , the number of irregular peaks within the first 2 ns time interval are increased by a factor of 3.2. In contrast, varying the pulse width of Φ AR shows no significant correlation with the number of irregular peaks. These results demonstrate that the delay of Φ AR should be controlled precisely for minimizing APP and improving the SPAD performance in high-speed photon counting applications.