A Pre-Selection–Enhanced Arbiter PUF for Strengthening PUF-Based Authentication

Physical Unclonable Functions (PUFs) have emerged as a compelling solution for hardware-based authentication, yet arbiter PUFs often require additional mechanisms to address reliability challenges and vulnerabilities to attacks. In this paper, we propose a Pre-Selection-based Enhanced Arbiter PUF that filters noise-induced bit flips through repeated sampling without imposing substantial hardware overhead. We evaluate our design via a two-step methodology: an initial screening on a subset of boards, followed by a comprehensive assessment on 56 Field Programmable Gate Arrays (FPGA) boards—yielding 336 million challenge-response pairs (CRPs). Our findings indicate that the Pre-Selection process notably boosts reliability, with median values rising from about 72.63% up to 89.60% under higher sampling conditions. Even with a broader spread in uniqueness (majorly near the ideal value), most devices remain within a practically acceptable range for authentication. Crucially, False Acceptance Rate (FAR) and False Rejection Rate (FRR) stay below or near 2.5% in most configurations, underscoring the approach’s real-world viability. Additionally, bit aliasing reaches near-excellent levels, whereas Bit Error Rate (BER) remains below 0.2 or 0.3 for most boards. Entropy estimation consistently exceeds 95%, verifying that Pre-Selection retains the global randomness essential for security. A modeling attack test using Artificial Neural Network (ANN) model further yielded near-random prediction accuracy (ranging from 50% - 56%), confirming that enhanced reliability does not compromise unpredictability. These results suggest that a lightweight, modular post-processing scheme can balance reliability, distinctiveness, and randomness in arbiter PUFs, offering a scalable pathway to secure authentication in resource-constrained devices.