FPGA-Accelerated Sparse Subset Segmentation Using ADMM for High-Resolution Imagery | Zendy

Rupali Karthikeyan | Zendy; Deep Amit Lodaya | Zendy; Rama Muni Reddy Yanamala | Zendy; Rayappa David Amar Raj | Zendy; K Krishna Prakasha | Zendy; T Subeesh | Zendy; V Anandkumar | Zendy; Archana Pallakonda | Zendy

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FPGA-Accelerated Sparse Subset Segmentation Using ADMM for High-Resolution Imagery

Author(s) -

Rupali Karthikeyan,

Deep Amit Lodaya,

Rama Muni Reddy Yanamala,

Rayappa David Amar Raj,

K Krishna Prakasha,

T Subeesh,

V Anandkumar,

Archana Pallakonda

Publication year - 2025

Publication title -

ieee access

Language(s) - English

Resource type - Magazines

SCImago Journal Rank - 0.587

H-Index - 127

eISSN - 2169-3536

DOI - 10.1109/access.2025.3590167

Subject(s) - aerospace , bioengineering , communication, networking and broadcast technologies , components, circuits, devices and systems , computing and processing , engineered materials, dielectrics and plasmas , engineering profession , fields, waves and electromagnetics , general topics for engineers , geoscience , nuclear engineering , photonics and electrooptics , power, energy and industry applications , robotics and control systems , signal processing and analysis , transportation

Applications in computer vision and image analysis, including object recognition and diagnostic imaging, are reliant on a fundamental competency in image segmentation. However, high-computation methods are occasionally exceeded by the energy economy and processing speed of typical CPU-based systems. To surpass these limitations, a hardware-accelerated picture segmentation method is introduced, leveraging the Alternating Direction Method of Multipliers (ADMM) technology, FPGA parallel processing, and sparse subset selection. ADMM algorithms are designed in high-level synthesis (HLS) C code for deployment on Xilinx Zynq UltraScale+ MPSoC. This approach simplifies hardware integration and maintains accuracy while reducing latency and improving energy efficiency. Significant energy savings and decreased execution times are indicated by experimental results, with FPGA achieving segmentation in 9 ms as opposed to 13 ms on a CPU, thereby proving the tremendous computational efficiency of FPGA-based solutions. These results demonstrate how hardware acceleration can enable scalable real-time applications in limited resources by overcoming computational constraints.

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