Dynamic Surrogate Optimization of Vertically Stacked Nanosheet FET Based on Gaussian Process Regression

While speed improvements are pivotal for advancing modern transistor technologies and ensuring faster computational performance, the tradeoffs with other critical electrical properties, such as threshold voltage ( V T ) and off-current ( I OFF ), are often overlooked. These tradeoffs can significantly impact the overall device performance. The design of vertically stacked n-type and p-type nanosheet FETs (NSFETs) was applied using a dynamic surrogate optimization-gaussian process regression (DSO-GPR) with batch assessment and halting conditions. A vertically stacked silicon-based system is created and refined. Source extension ( S ext ), drain extension ( D ext ), gate length ( L g ), nanosheet height ( NS h ), nanosheet width ( NS w ), and number of fin ( nfin ) make up the input variables. In addition to applying normalization to make the weight assignment to the goal functions easier, a penalty component was incorporated to manage the V T . This study demonstrates the effectiveness of the DSO-GPR framework in optimizing NSFET-based inverter designs by balancing speed, I OFF and V T . Among the three evaluated cases, case 1 achieved the fastest propagation delay (1.05 ps) due to higher I ON and lower V T , albeit with increased I OFF and V T mismatch. Case 2 provided a balanced trade-off, significantly reducing I OFF while maintaining a competitive delay of 1.25 ps and achieving V T matching at 0.11 V for both n-type and p-type NSFETs. The optimum parameters for n-type are L g = 5 nm, N Sh = 9 nm, N Sw = 42 nm, S ext = 3 nm and D ext = 4 nm, nfin = 5; for p-type, L g = 7 nm, N Sh = 10 nm, N Sw = 42 nm, S ext = 3 nm and D ext = 3 nm, nfin = 5. Case 3 minimized leakage at the cost of delay, highlighting the trade-off between power and performance. These results validate the framework’s adaptability and automation, with performance-based stopping criteria that balance accuracy and computational efficiency.