Open AccessAn Effective Method to Compensate for Testing Induced SBFET Degradation by Charging Deep-level Interface Trap
Author(s) -
Tiexin Zhang,
Fanyu Liu,
Lei Shu,
Siyuan Chen,
Yuchong Wang,
Yuchen Wu,
Jing Wan,
Yong Xu,
Shi Li,
Yuyang Ding,
Bo Li,
Zhengsheng Han,
Tianchun Ye
Publication year - 2025
Publication title -
ieee access
Language(s) - English
Resource type - Magazines
SCImago Journal Rank - 0.587
H-Index - 127
eISSN - 2169-3536
DOI - 10.1109/access.2025.3573406
Subject(s) - aerospace , bioengineering , communication, networking and broadcast technologies , components, circuits, devices and systems , computing and processing , engineered materials, dielectrics and plasmas , engineering profession , fields, waves and electromagnetics , general topics for engineers , geoscience , nuclear engineering , photonics and electrooptics , power, energy and industry applications , robotics and control systems , signal processing and analysis , transportation
In this paper, the threshold voltage ( V th ) of Schottky barrier field effect transistors (SBFETs) based on ultra-thin silicon on insulator (SOI) wafer shift induced by electrical test is analyzed. Repeated testing gives rise to a positive shift of the V th which is similar to the constant voltage stress effect found in two-dimensional material. The series resistance of Source and Drain ( R sd ), mobility (μ), and trapped charge are studied. The positive Δ V th is independent of the R sd and μ, but related to the deep-level acceptor interface trap which is charged during test. The main reason for trap charging is that the Source and Drain contact prepared by metal deposition cannot provide electrons for trap capturing before testing. In order to compensate the Δ V th induced by test, a deep-level trap charging method is proposed. The necessity of this new test method is verified by irradiation experiments.