Open AccessDFT based estimation of CNT parameters and simulation-study of GAA CNTFET for nano scale applications
Author(s) -
Bhupendra Bahadur Singh,
B. Prasad,
Dinesh Kumar
Publication year - 2020
Publication title -
materials research express
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.383
H-Index - 35
ISSN - 2053-1591
DOI - 10.1088/2053-1591/ab6924
Subject(s) - carbon nanotube field effect transistor , materials science , carbon nanotube , scaling , gate oxide , optoelectronics , nanotechnology , dielectric , node (physics) , nano , gate dielectric , channel (broadcasting) , field effect transistor , transistor , electrical engineering , physics , engineering , voltage , mathematics , geometry , quantum mechanics , composite material
The device dimensions have been consistently scaling down since many developing technologies need smaller and faster integrated circuits for advancement and improvement in both performance and device density. Device dimensions have been decreased drastically from micron to sub nanometer regime. Traditionally, miniaturizing and performance improvement was obtained by tweaking the MOSFET- reducing the channel lengths and gate oxide thickness, increasing dielectric constants etc Unfortunately at 22 nm node it reached a dead end. However, at 22 nm node the tri-gate FinFET introduced by Intel Corporation have provided many possibilities for scaling the dimensions with satisfactory device performance. Further, the gate all around (GAA) carbon nano tube field effect transistor (CNTFET) provides high gain, high trans-conductance, reduced short channel effects and conditions for scaling the technology to sub nano scale. Due to surround gate structure this GAA CNTFET offers better control with integration of high_k stacked dielectric wrapped around the channel. In this paper, first properties of Carbon nanotube (CNT) have been comprehensively studied for various chirality and diameter and parameters viz. Density of States (DoS) and Band gap (E g ) are extracted by using MedeA tool’s VASP 5.3 module. The various CNT chirality have been optimized and the extracted parameters used to model and simulate CNTFET using Silvaco’s Devedit3D, Atlas and Atlas3D modeling and simulation modules. The device input (I D -V GS ) and output (I D -V DS ) characteristics have been intensively studied and parameters including I ON /I OFF ratio, DIBL, sub threshold slope extracted and compared with the conventional devices. The GAA CNTFET device at 0.8 V supply voltage exhibits threshold voltage (V TH ) 0.254 V, drain induced barrier lowering (DIBL) 72 mV/V, sub-threshold swing (SS) 63.29 mV/dec, and I ON/ I OFF ratio 7.17e + 06. The results demonstrate improvement in device parameters for the GAA CNTFET device as compared to bulk silicon and FinFET devices.