Open AccessDesign of 12T SRAM cell for low power dissipation
Author(s) -
Suresh Kumar R,
K. Ranjani,
A Rasheedha
Publication year - 2020
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/994/1/012045
Subject(s) - static random access memory , standby power , computer science , embedded system , cmos , transistor , robustness (evolution) , dissipation , electronic engineering , leakage (economics) , low power electronics , power (physics) , voltage , electrical engineering , computer hardware , power consumption , engineering , physics , quantum mechanics , thermodynamics , biochemistry , chemistry , macroeconomics , economics , gene
The present semiconductor industry is developing quite quickly. Mobile and portable devices are becoming small for each day and moreover there is a rising demand for extended battery power. With these demands it is significant for researchers to emphasis on the leakage capacity in standby mode. For the exact communication, SRAM was intended with DSP, processor and applications with low power devices. The design engineer emphases mostly on the making of low energy consuming, higher bandwidth and large memory capacity. Memory is an essential part of majority of these systems as well asit is also reduced as the system size reduces. High processing architecture as well as low power is consequently a foremost concern. The robustness of static random access memory cells is other important factor. This paper proposed the architecture design of 12T SRAM for the reduction minimization of power leakages or power consumption during the sleep transistor. This supports in the minimization of the leakage in the CMOS transistor. Based on the parameters like write delay, read delay, write voltage, read voltage, and power consumption at various temperature are compared to the existing SRAM architecture of 6T, 7T and 8T, we acquire reduced power consumption in the proposed 12T SRAM architecture..