Open AccessPower Optimization by Using Reconfigurable LFSR with Gated Clock
Author(s) -
S. Anandhi,
R. Neela,
M. Janaki Rani
Publication year - 2020
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.179
H-Index - 26
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/993/1/012065
Subject(s) - very large scale integration , shift register , fault coverage , computer science , clock gating , electronic circuit , linear feedback shift register , built in self test , embedded system , power consumption , computer hardware , power (physics) , electronic engineering , test compression , automatic test pattern generation , engineering , clock signal , clock skew , electrical engineering , physics , quantum mechanics
LFSR are the most commonly used test pattern generators due to its efficiency than any binary counters. This paper presents the design of a novel reconfigurable LFSR with clock gating for VLSI testing. The technology advancement in VLSI has increased the complexity of chip testing. This complexity in testing has made the Logic BIST (LBIST) more popular than Automatic Test Equipment. This helps the testing with an additional hardware added inside the circuit. ATE does not apply any test patterns but the test patterns are generated by the testing circuits which are inbuilt in the hardware. Thus the cost of testing is greatly reduced. In the LBIST, reconfigurable LFSR are used for the test pattern generation which improves the fault coverage in IC testing. This increases the generation of random test pattern. To increase the speed of testing and reduce the power required a clock gating is introduced in the reconfigurable LFSR. In traditional testing more transistors are required in the circuits resulting in consumption of more power than power required for the functioning of the circuit. Conventional clock circuit consumes 70% of the clock buffer. This reduces the number of switching activities in the BIST. The power consumption of the proposed reconfigurable LFSR with gated clocking is significantly reduced when compared with the conventional LFSR with clocking circuits.