Open AccessDesign of Parallel Prefix Adder and Subtractor using Majority Logic Formulations
Author(s) -
Divya Gampala,
L. Srinivas,
Vaseem Ahmed Qureshi
Publication year - 2020
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/981/4/042077
Subject(s) - adder , subtractor , computer science , logic gate , arithmetic , carry save adder , mathematics , algorithm , telecommunications , latency (audio)
The New Technology is quantum dot cellular automata at Nano metric scale, which has more focal points like lower area (PLBs) requirement and low Power Consumption. It can not be smaller than the present size transistors. The QCA solution applies to one of the alternative ways to resolve this physical edge. We generated AND gate, OR gate and NOT gate with this QCA invention. With the availability of universal gates in this article, we are allowed to execute any digital logic operation by using majority gates, which have the highest quality class contestant features and achieve the best area lap-delay compromise, such as Brent-Kung Adder(BKA), Kogge stone Adder(KSA), ladner fischer adder(KSA). At last, the adjustments such as delay (speed), power usage, field, ADP and PDP were considered.