Open AccessArea-Delay-Power analysis of Carry Look-AheadAdder Architecture
Author(s) -
Ch. Rajendra Prasad,
Y. Srikanth,
P. Ramchandar Rao,
S. Sanjay Kumar
Publication year - 2020
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/981/3/032022
Subject(s) - adder , carry (investment) , computer science , microprocessor , carry save adder , architecture , computer hardware , digital signal processing , power (physics) , serial binary adder , look ahead , power–delay product , propagation delay , computer architecture , telecommunications , latency (audio) , computer network , algorithm , art , physics , finance , quantum mechanics , economics , visual arts
The addition is common in hardware for the microprocessor and digital signal processor (DSP), and an adder is used to execute the addition. The Adder should feature high speed and low power for real-time applications. An effective adder architecture principally advances the performance of microprocessors and DSP systems. The carry propagation delay (CPD) is the main apprehension in the design of adder architecture. To address CPD, a new Carry Look-Ahead architecture is proposed, in which the carry propagation is scheduled before the calculation of the final sum using carry look–ahead (CLA) method. A quantitative estimate shows that the Area Delay Product (ADP) of proposed adder architecture is minimized by 10% as compared with the existing adders’ architectures.