Open AccessPrinciple of constructing flat designs of electronic circuit diagrams considering forbidden figures
Author(s) -
V. I. Potapov,
V. V. Suskin,
S. V. Filatkin
Publication year - 2020
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/971/5/052020
Subject(s) - printed circuit board , planarity testing , computer science , graph , electronic circuit , circuit design , commutation , circuit extraction , algorithm , circuit diagram , theoretical computer science , topology (electrical circuits) , engineering drawing , equivalent circuit , mathematics , electronic engineering , electrical engineering , engineering , embedded system , combinatorics , voltage , operating system
The problem of designing double-sided printed circuit boards in the form of synthesis of flat structures of electronic circuit diagrams at the design stage is considered. The aim of the work is to arrange the connections on two sides of the printed circuit board without jumpers, which facilitates the conditions for routes to any tracer of modern design programs. The main drawback of all the algorithms used is the principle of sequential and fragmented viewing of the commutation space incorporated in them. To solve this problem, it is necessary to use the graph theoretical method, rather than the topographic method, where priority is given to the metric aspect of the problem. The graph theoretical method involves preliminary stratification of the graph on two sides of the printed circuit board and analysis of the planarity of the graph circuit with subsequent elimination of jumpers, assigning a conflict link of the route to the back of the circuit board.