Open AccessSpeed and Area Efficient FXP Adders and Multipliers: A Comparative Analysis for LNS System
Author(s) -
Muhammad Sufyan Safwan Mohamad Basir,
Rizalafande Che Ismail,
Siti Zarina Md Naziri,
Mohd Nazrin Md Isa,
Sohiful Anuar Zainol Murad,
A. Harun
Publication year - 2020
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/932/1/012061
Subject(s) - adder , multiplier (economics) , verilog , computer science , latency (audio) , carry save adder , parallel computing , cmos , computer hardware , arithmetic , logarithm , field programmable gate array , electronic engineering , mathematics , engineering , telecommunications , economics , macroeconomics , mathematical analysis
In this paper, a variety of adder and multiplier are compared to be implemented in a new logarithmic number system (LNS). Both adder and multiplier are designed with a generic very high-speed integrated circuit hardware description language (Verilog) program. This makes it possible to achieve the optimum performance in latency and area of 0.18µm CMOS technologies LNS chip. Consequently, the optimal configurations vary with speed and area of the schemes and in some cases can be compact area, O ( n ), fast in latency O( log 2 n) or optimized. The program was scripted based on fixed-point (FXP) adders and multipliers that yet will be implemented in LNS system. The functionality of the scheme was tested before synthesized. Outcomes show that Ladner Fisher (LF) adder and modified Baugh Wooley multiplier contribute to fast in latency and consume minimal area.