Open AccessHybrid Floating Point/Logarithmic Number System Processor
Author(s) -
Caiwang Sheng,
Rizalafande Che Ismail,
Siti Zarina Md Naziri,
Mohd Nazrin Md Isa,
Sohiful Anuar Zainol Murad,
A. Harun
Publication year - 2020
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/932/1/012059
Subject(s) - computer science , compiler , verilog , floating point , parallel computing , multiplication (music) , floating point unit , computer hardware , single precision floating point format , subtraction , logarithm , computation , arithmetic , field programmable gate array , algorithm , mathematics , operating system , combinatorics , mathematical analysis
Hybrid Floating Point/Logarithmic Number System processor is an Arithmetic Logic Unit with hybrid architecture in which its data computation involves Floating Point (FLP) and Logarithmic Number System (LNS). LNS processor has high performance but requires complicated hardware to support its function, especially LNS addition and subtraction. Therefore, hybrid processor is proposed to perform multiplication/division in LNS, addition/subtraction in FLP. Through merging FLP and LNS, data computation can be done in a faster, precise and less complicated way. The proposed research is a 32-bit Hybrid FLP/LNS processor, which involving 32-bit fixed point data format and 32-bit single precision FLP format. The EDA tools used in developing and simulating this project is based on Synopsys Design Compiler and Altera Quartus II, and the Hardware Description Language used is Verilog HDL. Logical synthesis of this project is done by using Synopsys Design Compiler and its area, timing and power are validated.