Open Access8-Bit NCL Asynchronous Multiplier based on Radix-4 Booth Algorithm
Author(s) -
Weixiang Deng,
Wenxiang Cheng,
Jie Cheng,
Ling Ni,
Anping He
Publication year - 2020
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/914/1/012024
Subject(s) - multiplier (economics) , computer science , robustness (evolution) , arithmetic , asynchronous communication , algorithm , computer hardware , booth's multiplication algorithm , adder , parallel computing , mathematics , computer network , telecommunications , biochemistry , chemistry , macroeconomics , economics , gene , latency (audio)
Multiplier is one of the key modules in signal processing circuit and processor, and its robustness is especially important in the complex environment. Due to the lack of robustness of single-rail logic, a Null Convention Logic (NCL) Multiplier based on the Radix-4 Booth 8-bit fast parallel structure is proposed in this paper. The Radix-4 Booth algorithm reduces the number of partial products to lower the computing time, and the “sign generate” algorithm simplifies sign extension bitcomputation. In order to demonstrate the effectiveness of the proposed hardware implementation scheme, we implement an improved 8-bit NCL multiplier on vivado platform, the speed of which is 14% higher than that of the traditional Wallace NCL 8bit multiplier.