Open AccessReducing noises of high-speed Bi-JFET charge-sensitive amplifiers during schematic design
Author(s) -
О. В. Дворников,
Vladimir A. Tchekhovski,
N. Prokopenko,
I. V. Pakhomov
Publication year - 2020
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/862/2/022068
Subject(s) - jfet , schematic , amplifier , transistor , electronic circuit , noise (video) , materials science , electrical engineering , optoelectronics , transistor array , field effect transistor , electronic engineering , computer science , voltage , engineering , cmos , artificial intelligence , image (mathematics)
The technique of circuit noise reduction of charge-sensitive amplifiers containing bipolar and junction field-effect transistors is considered. The initial and improved circuit of the integrated charge-sensitive amplifiers using the above mentioned technique, the results of the step-by-step noise reduction when changing the sizes and operating modes of transistors, and improvement of the bias circuits are presented.