Open AccessHigh throughput and variable temperature superconductor integrated circuit test and evaluation using ICE-T
Author(s) -
Anubhav Sahu,
Benjamin Chonigman,
Andrei Talalaevskii,
В. В. Доценко,
Steven Ruotolo,
Jia Tang,
Deepnarayan Gupta
Publication year - 2020
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/756/1/012012
Subject(s) - testbed , integrated circuit , chip , robustness (evolution) , electronics , megabit , wafer , digital electronics , cryocooler , computer science , materials science , electronic circuit , electronic engineering , optoelectronics , electrical engineering , mechanical engineering , engineering , chemistry , computer network , biochemistry , gene
Superconductor digital integrated circuits (ICs) require rapid evaluation of multiple copies to obtain statistical operational data. These data are used for assessing model-to-hardware correlation and facilitate iterative IC design development. The Integrated Cryogenic Electronics Testbed (ICE-T) is a cryogen-free test platform, which can test multiple chips simultaneously with similar convenience to a liquid-helium immersion probe and with cooldown times of between 3.3 to 4.5 hours. We have developed a three-chip insert to increase the volume of chip testing and demonstrated simultaneous cooling of six chips with two such inserts. We report the test statistics collected from 27 chips across a single wafer. We have also used the ICE-T’s convenient temperature control system to evaluate chips in the 3.5 - 6 K range. Such evaluation determines the robustness of circuit design and its tolerance to critical current fluctuations due to fabrication variation.