Open AccessLow Cost Histogram Implementation for Image Processing using FPGA
Author(s) -
Dua’a Basman Younis,
Basma Mk. Younis
Publication year - 2020
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.179
H-Index - 26
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/745/1/012044
Subject(s) - histogram , matlab , field programmable gate array , computer science , pixel , histogram matching , plot (graphics) , image processing , image (mathematics) , image histogram , artificial intelligence , computer vision , algorithm , computer hardware , mathematics , binary image , statistics , operating system
The solution for various applications of industrial programmed testing is image processing. In spite of this, if the contents of the image are not available in an appropriate format, even the most complex algorithms cannot extract the right information, via using a histogram, the image content can be easily processed. In this paper a histogram construction hardware that it can be able to create a histogram for different types of gray scale images of different sizes, is presented which gives accurately equivalent data as derived from a histogram plot using ISE simulator and MATLAB. By taking benefit of the high-level features of the Spartan3EXC3S500E FPGA architectures and Artix-7XC7A100T, the execution time for the proposed design is 156 times faster than MATLAB time for (16×16) pixel image size in XC3S500E and it is 6 in the worst case. Also, the execution time for the proposed design is 236 times faster than MATLAB time for (16×16) (16×16) pixel image size in XC7A100T and it is 8 in the worst case. The maximum frequency resulted and the maximum number of resources used in XC3S500E is 160.411 MHz, 45% respectively. While the maximum frequency resulted and the maximum number of resources used in XC7A100T is 216.685MHz, 59 %.