Open AccessDesign of a High Resolution TDC Based on Multi-channel
Author(s) -
Qingsong Zhang,
XU Guang-hui,
Na Li
Publication year - 2019
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/569/3/032008
Subject(s) - field programmable gate array , computer science , differential nonlinearity , computer hardware , chip , carry (investment) , nonlinear system , code (set theory) , time to digital converter , key (lock) , electronic engineering , embedded system , engineering , telecommunications , least significant bit , physics , set (abstract data type) , finance , jitter , quantum mechanics , clock signal , economics , programming language , operating system , computer security
In this paper, a high precision time digital converter (TDC) system is designed based on Xilinx 7 series FPGA chip, which includes fine time measurement module, logic control module, rough count module and display module. The key point of FPGA TDC design is that there are a large number of delay units in the underlying hardware resources with stable delay. A delay chain consisting of 64 fast carry chains (CARRY4) is constructed by using the CARRY4 module inherent in the chip. In addition, the code density method is used to solve the nonlinear problem of internal special carry chain delay unit, effectively eliminate the error caused by wiring path, and reduce the integral nonlinear and differential nonlinear error. The experimental results show that the code density method can accurately reflect the distribution of delay time.