Open AccessLow Power Memory System Design Using Power Gated SRAM Cell
Author(s) -
Srijani Pal,
Divya S. Salimath,
Banusha Chandran,
A. Anita Angeline,
V. S. Kanchana Bhaaskaran
Publication year - 2021
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/1187/1/012008
Subject(s) - static random access memory , computer science , transmission gate , cmos , embedded system , transmission (telecommunications) , cpu cache , electronic engineering , cache , semiconductor memory , computer hardware , transistor , electrical engineering , engineering , voltage , parallel computing , telecommunications
Static Random-Access Memory (SRAM) is widely used in cache memory, microprocessors, general computing applications and electronic circuits involving ASIC, FPGA and CPLD. The most commonly used SRAM is the 6T SRAM. However, it incurs higher power consumption and degraded signal to noise margin (SNM) during write and read operations. To overcome these shortcomings, a single ended power gated 11T SRAM for low power operation is proposed. The power consumption reduction is achieved using power gating through virtual VSS (VVSS) signal and transmission gates. Due to the introduction of transmission gates, memory cells realize enhanced write margin characteristics as compared to existing technologies. The proposed cell realizes 33.33% lower power consumption and 50% improvement in read SNM as compared to existing SRAM technologies. To study the impact of technology scaling on our proposed design, the work is carried out in Cadence Virtuoso® tool using both 180nm CMOS technology and BPTM 32nm FinFET technology.