Open AccessLow Power Single-Bit Cache Memory Architecture
Author(s) -
Reeya Agrawal,
Neetu Faujdar,
Aditi Saxena
Publication year - 2021
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/1116/1/012136
Subject(s) - sense amplifier , cache , static random access memory , computer science , cache only memory architecture , cache pollution , parallel computing , cache coloring , cpu cache , memory architecture , semiconductor memory , computer hardware , cache algorithms , embedded system , computer architecture
A quantitative and yield analysis of single bit cache memory architecture has been analyzed. A single bit cache memory architecture is made up of a write driver circuit, SRAM cell, and sense amplifier. Apart from it, the power reduction technique has been applied over different blocks of single bit cache memory architecture such as sense amplifier and SRAM cell, to optimize the power consumption of the circuit. To check the robustness of the circuit monte Carlo simulation and process corner simulation also have been done. The conclusion arises that Single bit cache memory architecture having VMSA with forced stack technique over SRAM in an architecture consumes the lowest power (9.18 μW).