Open AccessReduce the Resources Utilization of LDPC Decoder Based on Min-Sum Decoder for Spread Spectrum Applications
Author(s) -
Mahmood F. Mosleh,
Fadhil Sahib Hasan,
Aya H. Abdulhameed
Publication year - 2021
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/1105/1/012033
Subject(s) - low density parity check code , computer science , field programmable gate array , bit error rate , decoding methods , additive white gaussian noise , soft decision decoder , chaotic , communications system , forward error correction , keying , encoder , algorithm , error detection and correction , electronic engineering , computer hardware , channel (broadcasting) , telecommunications , engineering , artificial intelligence , operating system
Communications with spread spectrum (SS) have attracted attention because of their channel attenuation immunity and low potential for interception. Aside from some extra features such as basic transceiver structures, the analogy alternative to digital SS systems would be chaotic communication. In this brief, Differential Chaos Shift Keying (DCSK) systems, non-periodic and random characteristics among chaos carriers and their interaction with soft data are designed based on low-density parity-check ( LDPC) codes. Because of simple structure and magnificent error correction capability. Using the development kit Xilinx kintex7 FPGA, we investigate the DCSK communication system’s hardware efficiency and resource requirement tendencies based on the LDPC decoding algorithm Min-Sum over AWGN channel. The results demonstrate that the proposed system model has major improvements in Bit Error Rate ( BER) performance and the real-time process. The Min-Sum decoder has comparatively fewer FPGA resources than other decoders for soft decisions. The implemented system achieves a coding gain of 10-4 BER efficiency with 5.6 dB associate Eb/No.