Open AccessModelling of Parallel Unsigned 2n-1 Modular Arithmetic Multiplier for RNS
Author(s) -
S Elango,
P. Sampath,
Sajan P. Philip,
S. Raja Sekar
Publication year - 2021
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/1084/1/012060
Subject(s) - modulo , residue number system , arithmetic , multiplier (economics) , very large scale integration , computer science , modular arithmetic , application specific integrated circuit , modular design , parallel computing , computation , field programmable gate array , cmos , computer hardware , mathematics , embedded system , algorithm , discrete mathematics , electronic engineering , economics , macroeconomics , engineering , operating system
Modular Multiplication operations are widely used in Digital crypto processors. Modulo multipliers is an essential block for Residue Number System (RNS) computation. Pointing to increase the performance of the RNS computation, the parallel unsigned modulo multiplier for 2 n -1 moduli is designed. A mathematical modelling, VLSI architecture and real-time verification are done in this work. Further, the modulo multipliers are described usingVerilog HDL, and the synthesize results for both FPGA and ASIC technologies are presented. Comparison is made based on the parameters such as Area, Power, Delay, PDP& ADP using Cadence RTL Compiler with 180 nm, 90 nm and 45 nm TSMC CMOS Technologies.From the analysis indicate that the proposed multiplier provides a 16% area reduction and 40% speed improvement with a better PDP and ADP performance compared tothe existing modulo multipliers. Finally, the usefulness of 2 n -1 modulo multiplier in RNS environment is discussed.