Open AccessPower reduction using high speed with saving mode clock gating technique
Author(s) -
Maan Hameed,
Hussein Sh. Mogheer,
Ali Mansour
Publication year - 2021
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/1076/1/012055
Subject(s) - clock gating , cpu multiplier , digital clock manager , clock domain crossing , clock skew , clock signal , computer science , clock network , modelsim , verilog , clock synchronization , computer hardware , synchronization (alternating current) , clock rate , clock drift , embedded system , field programmable gate array , synchronous circuit , jitter , channel (broadcasting) , vhdl , telecommunications , chip
The demand for low power consumption is motivated by several factors such as the evolution of portable design, reliability effects, and flexibility. The purpose of clock gating is inactive or suppresses change to fragments of the clock route as flip-flop, clock system and rationality under a specific condition processed by clock gating chips. Moreover, the clock is disabled when it is not necessary in clock gating to decrease power dissipation. Clock technique successfully turns off the clock any place it pointlessly expends power. By following the expressed methodology, the force utilization turns out to be less up to half without influencing the performance of the structure. The extraordinary source of power utilization is the clock. Clock signal is not used to achieve any digital calculation. It is for the most part utilized for synchronization of successive circuits. In this way, clock signal does not carry any data. In this research paper, a new sub module for high speed and saving mode is proposed. It saves more power by switch on only the target module and switch other module off. By using this technique, it may reduce power dissipation up to half. In order to execute encoder and decoder structure, the models of compression and decompression process is created by applying Verilog HDL language Quartus II 11.1 Web Edition with 32-Bit. In addition, operational simulation is executed by using ModelSim-Altera 10.0c (Quartus II 11.1 Starter Edition).