Open AccessImpact of interfacial layer thickness on gate stack-based DGTFET: an analog/RF prospective
Author(s) -
Vibhu Goyal,
Shubham Tayal,
Shweta Meena,
Ravi Gupta
Publication year - 2021
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/1070/1/012081
Subject(s) - stack (abstract data type) , materials science , layer (electronics) , optoelectronics , composite material , computer science , programming language
In this work, influence of interfacial layer thickness on gate-stack based double gate (DG) TFET device concerning analog/RF performance has been studied. Through simulation, it has been found that thicker interfacial layer can be used to mitigate the deprivation inRF/analog performance instigated with high - K gate dielectric. In this article, we have varied the thickness (Ti) of interfacial layer ranging from 0.2 nm to0.7nm and analyzed its effect. The decline in the intrinsic dc gain (δA V = Av (K = 3.9) - Av (K = 40) ), maximum oscillation frequency (δf MAX = fMAX (K = 3.9) - fmax (K = 40) ) and the cut -off frequency (Af T = f T(K = 39) - f T(K = 40) ) is 27.1 dB, 8 GHz and 6.4 GHz, respectively for T I = 0.2nm and24 dB, 1.7 GHz,&3.5 GHz, respectively in case ofT I = 0.7nm which indicates that if interfacial layer is thick (0.7nm), then, it is advantageous as compared to thickness of 0.2nm. Thus, such a device design not only decreases the surface lattice mismatching effect, but also, is more promising for better analog/RF performance of TFET device.