Open AccessComparison between CMOS full adder and PTL full adder
Author(s) -
M. Amitha,
Deepa
Publication year - 2021
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/1065/1/012047
Subject(s) - adder , cmos , dissipation , computer science , transistor , electronic engineering , electronic circuit , computer hardware , electrical engineering , engineering , physics , voltage , thermodynamics
In electronic industry the level of integration is an important aspect as makes the electronic device simpler and more reliable. The device density increases with the better level of integration. Power dissipation, area occupied and delay are some of the important factors that need to be considered. These parameters play a vital role in manufacturing portable electronic gadgets. Designing of full adder using conventional CMOS design and PTL has been shown in this paper. A comparison is made between the two designs with respect to power dissipation, delay and area (number of transistors). Mentor Graphics Tool is used in design and simulation of the full adder. The PTL full adder has a smaller number of transistors and lower power dissipation compared to CMOS full adder. With all the comparison made it will be concluded that the PTL full adder performance is better than the CMOS full adder.