Open AccessAn algorithmic approach for minimizing test power in VLSI circuits
Author(s) -
J. Poornimasre,
Harikumar Rajaguru
Publication year - 2021
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/1059/1/012039
Subject(s) - benchmark (surveying) , very large scale integration , computer science , set (abstract data type) , algorithm , test set , electronic circuit , power (physics) , value (mathematics) , test (biology) , automatic test pattern generation , function (biology) , parallel computing , computer engineering , embedded system , engineering , electrical engineering , artificial intelligence , paleontology , physics , geodesy , quantum mechanics , machine learning , evolutionary biology , biology , programming language , geography
Testing is an approach to check the function of the circuit or device under the test after its fabrication. To test the device, test patterns are required. The test patterns can be generated with the help of EDA tool. Those patterns having huge number of unfilled bits. The unfilled bits need to be assigned with certain logical value. This paper proposed two new algorithms. First algorithm assigns the unfilled bits with effective logical value and second algorithm change the order of test set and both algorithms aims to reduce the test power. Investigation on benchmark circuits shows that, the results of proposed algorithms effectively reduces the test power.