Open AccessDesign and analysis of High-Speed Low-Power Vedic Multiplier with 3-1-1-2 compressor Using Reversible Logic gates
Author(s) -
S. Dharani,
Abin Satheesan,
M. A. Asuvanti,
Ranjith Kumar,
S. Vidhya
Publication year - 2021
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/1059/1/012024
Subject(s) - fast fourier transform , computer science , multiplier (economics) , adder , power–delay product , arithmetic , logic gate , computer hardware , digital signal processing , propagation delay , delay calculation , algorithm , mathematics , telecommunications , latency (audio) , computer network , economics , macroeconomics
The FFT Function in digital signal processing is one of the most important function in several applications such as Image Processing, Wireless Communications and Multimedia. FFT Processors consisting of butterfly structure operations involving necessary operations such as Addition, Subtraction, and Multiplication of complex values. The FFT Butterfly Structure work is designed with a “Vedic Multipliers” for applications at high speed. In this Vedic Multiplier, an algorithm called “Urdhva Triyabhyam” was used to improve its efficiency by optimizing the number of logic gates, constant inputs and garbage outputs. The Data Computation time is reduced by an 3-1-1-2 compressor using reversible logic gates. Hence reducing the surplus power consumption of 11.24% and summation of the partial products is done with less delay factor of about 5.28%. The area, power, delay, area delay product and power delay product are calculated using cadence virtuoso and is implemented in Spartan-6 device family using Xilinx ISE.