Open AccessDesign and process features of CMOS SOI transistors with increased tolerance to the total dose
Author(s) -
Dmitriy A. Lagaev,
A.S. Klyuchnikov,
Н. А. Шелепин
Publication year - 2021
Publication title -
iop conference series. materials science and engineering
Language(s) - English
Resource type - Journals
eISSN - 1757-899X
pISSN - 1757-8981
DOI - 10.1088/1757-899x/1047/1/012111
Subject(s) - silicon on insulator , cmos , microelectronics , transistor , node (physics) , radiation hardening , electronic engineering , electronic circuit , very large scale integration , process (computing) , integrated circuit , materials science , electrical engineering , computer science , optoelectronics , engineering , silicon , detector , voltage , structural engineering , operating system
The paper considers methods to improve integrated circuits’ tolerance based on the SOI CMOS technology to total dose radiation. The main effects that occur in SOI CMOS transistors as a result of radiation response with the VLSI are discussed. The final part of the work demonstrated the main methods that make it possible to increase the radiation hardness of ICs based on the SOI CMOS technology. The advantages and disadvantages of each technique will be discussed. The prospects for developing microelectronics products with increased tolerance to external influences will be analyzed under constant process node scaling.