Open AccessDesign and application of digital phase locked loop based on Quartus II
Author(s) -
Yongchun Xie,
Jin Zhou,
Shengwu Kang
Publication year - 2020
Publication title -
iop conference series. earth and environmental science
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.179
H-Index - 26
eISSN - 1755-1307
pISSN - 1755-1315
DOI - 10.1088/1755-1315/617/1/012026
Subject(s) - phase locked loop , dpll algorithm , pll multibit , computer science , electronic engineering , bandwidth (computing) , frequency divider , engineering , jitter , telecommunications , cmos
The traditional phase locked loop (PLL) is realized by analog circuit. Compared with PLL realized by traditional analog circuit, digital phase locked loop (DPLL) has the advantages of high precision, not affected by temperature and voltage, adjustable loop bandwidth and center frequency, and easy to construct high-order PLL. With the rapid development of communication technology and integrated circuit technology, DPLL will be more widely used. In this paper, the PLL macroblock is used to design and realize the functions of frequency division, frequency doubling and phase locking in Quartus II development environment. The validity of the design and application of the DPLL is verified by practical verification.