Open AccessA low jitter all - digital phase - locked loop in 180 nm CMOS technology
Author(s) -
O. V. Shumkin,
Vladimir Butuzov,
D. Normanov,
P. Ivanov
Publication year - 2016
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/675/4/042042
Subject(s) - phase locked loop , jitter , cmos , digitally controlled oscillator , electronic engineering , loop (graph theory) , delay locked loop , phase noise , chip , computer science , block (permutation group theory) , engineering , delay line oscillator , telecommunications , mathematics , geometry , combinatorics