z-logo
open-access-imgOpen Access
Physical limits for scaling of integrated circuits
Author(s) -
Waldemar Nawrocki
Publication year - 2010
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/248/1/012059
Subject(s) - miniaturization , electronic circuit , cmos , integrated circuit , scaling , semiconductor device fabrication , electrical engineering , transistor , electronic engineering , electronics , computer science , engineering , voltage , mathematics , geometry , wafer

The content you want is available to Zendy users.

Already have an account? Click here to sign in.
Having issues? You can contact us here