Open AccessTile-based multiple parallel triangle rasterization algorithm implemented in FPGA
Author(s) -
Jian Xue,
Dihan Ai,
Mingjiang Wang
Publication year - 2022
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/2253/1/012015
Subject(s) - computer science , tree traversal , modelsim , algorithm , midpoint , rendering (computer graphics) , field programmable gate array , computer graphics (images) , computer hardware , mathematics , vhdl , geometry
With the progress of rendering technology, the industry has put forward higher requirements for GPU performance while rasterization algorithm plays an important role in GPU performance. In this paper, we first review some of the current mainstream rasterization algorithms. Then we propose a triangle rasterization algorithm—tile-based multiple parallel midpoint rasterization algorithm. This algorithm combines the characteristics of midpoint traversal and tiled traversal. At last, we use FPGA to implement the algorithm in order to verify the feasibility of the algorithm. And we use the triangle data set used in previous papers to simulate in Modelsim software. The results show that this algorithm can improve the rasterization speed and the highest frequency of this design is 200MHZ.