Open AccessDesign of Low Parasitic Inductance SiC MOSFETs Halfbridge Power Modules
Author(s) -
Yifan Wang,
Jie Gong,
Qihua Song,
Li Luo,
Bin Zhang,
Qing Guo
Publication year - 2022
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/2224/1/012120
Subject(s) - parasitic element , inductance , parasitic extraction , power module , power (physics) , software , electrical engineering , topology (electrical circuits) , finite element method , electronic engineering , computer science , engineering , physics , voltage , structural engineering , quantum mechanics , programming language
The working mechanism of a half-bridge SiC MOSFETs two chips parallel module is studied. Its parasitic inductance of the power module is simulated by using the Ansoft Q3D Extractor software, and its heat transfer mechanism is simulated using the finite element software ANSYS software. Aiming at reducing the parasitic inductance, a new topology of power chips inside the module is designed, which places the chips that are in the same working circuit loop in close vicinity to reduce the whole circuit length and area. Meanwhile, the thermal characteristics are also analyzed. Considering the factors of parasitic inductance and heat dissipation, the optimal module design scheme is finally determined.