Open AccessFault-tolerant architecture for Cache : Summaries, Assessments and Trends
Author(s) -
Xuru Wang,
Xin Gao,
Zongnan Liang,
Jiawei Nian,
Hongjin Liu
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/2113/1/012068
Subject(s) - cache , computer science , latency (audio) , cache algorithms , power consumption , fault tolerance , architecture , reliability (semiconductor) , key (lock) , reliability engineering , embedded system , cpu cache , parallel computing , power (physics) , distributed computing , operating system , engineering , art , telecommunications , physics , quantum mechanics , visual arts
Fault-tolerant design of cache is a key aspect of highly reliable processor design. In this paper, based on the key metrics in Cache architecture design: reliability, power consumption, latency and area, we divided the related research into two categories: one is to maximize reliability with guaranteed latency, power consumption and area, the other is to minimize latency, power consumption and area loss while ensuring fault tolerance reliability. Based on the classification, by analyzing different studies of Data and Tag in Cache, this paper gives the characteristics of these methods and the future development trend.