Open AccessThe High-Speed Low-Power Dynamic Comparator
Author(s) -
Miao Cao,
Weixun Tang
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/2113/1/012064
Subject(s) - comparator , preamplifier , comparator applications , pmos logic , computer science , transistor , electronic engineering , offset (computer science) , electrical engineering , power (physics) , nmos logic , voltage , engineering , cmos , physics , amplifier , quantum mechanics , programming language
This paper comments on four works for the optimization of comparator design. Today, with the development of integrated circuits, the requirements for comparators about low power, low delay, few offset voltage, and low noise are highly desirable. Specifically, these works made progress in the conventional comparator, which comprises a preamplifier and a latch. They also solved some problems, such as decreasing power and delay. Some works employ a positive feedback cross-coupled pares to provide a larger gain in the preamplifier, use PMOS switch transistors to accelerate the definition phase, or a double-tail architecture to increase the latch regeneration speed. Other work designs a charge pump to improve speed.