Open AccessA High Speed Redundant IO Bus for Energy Power Controller System
Author(s) -
Qinghui Lou,
Luming Sun,
Haisong Lu,
Weifeng Xu,
Zhebei Wang,
Cai Dan,
Xiangjian Shi
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/2113/1/012024
Subject(s) - computer science , synchronizing , field programmable gate array , can bus , embedded system , computer hardware , controller (irrigation) , register file , real time computing , instruction set , telecommunications , transmission (telecommunications) , agronomy , biology
This paper designs and implements a High Speed Redundant IO Bus for Energy Power Controller System. The physical layer adopts multi-point low-voltage differential signal standard. This bus has the characteristics of high real-time, high throughput and easy expansion. The controller communicates with IO module by A/B bus alternately, monitors link status in real time and collects IO module data. Non real time slots can be used to control non real time messages for IO modules such as time synchronizing and memory monitoring. The controller ARM core runs QNX real-time operating system, and transmits the message needed to communicate with IO modules to the FPGA through DMA. After receiving the message, the FPGA parses the message and automatically fills in the CRC check code and frame end flag at the end of the message. When the FPGA receives the data feedback from the IO module, it performs CRC verification. If the verification passes, it fills the corresponding module receiving buffer. Otherwise, it fills the CRC verification error flag in the register of the corresponding IO module to reduce the load of the arm core.