Open AccessIMPLEMENTATION OF ELECTRONIC DEVICES OF CMOS FULL ADDER IN LOW POWER VLSI CIRCUITS
Author(s) -
P. Durgaprasadarao,
K. V. Daya Sagar
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/2089/1/012081
Subject(s) - adder , cmos , electrical engineering , computer science , electronic circuit , very large scale integration , chip , low power electronics , electronic engineering , power (physics) , embedded system , engineering , power consumption , physics , quantum mechanics
Battery-powered devices (for example, mobile phones, digital personal aids, etc) are increasing on the mobile electronic systems market by developing microelectronic circuits with low energy dissipation. The problem of dissipating power could limit the flexibility of the computer system, as the chip’s density and complexity keep on increasing. The power supply consumes approximately 35% of the chip power, particularly at the nanometer level. The purpose of this project is to investigate the efficiency of one of the most reliable low power concepts called Power Gating. It is only nanometer-scale CMOS devices that are the most common technology in existing VLSI systems. Leakage power has become an integral component of total power in the nanometer technology regime. The ALU’s basic feature unit is Full Adder. The electricity consumption of an ALU is decreased by decreasing the energy consumption of an ALU, and an ALU will reduce the power consumption by decreasing the total power consumption. So these days, the complete adder designs are becoming more common with low power characteristics. The proposed project shows the concept of the micro wind tool for low power less transistors.