Open AccessDesign of High Speed and Area Efficient Finite Field Multiplier Using Factoring Technique for Communication
Author(s) -
S Baba Fariddin,
Rahul Mishra
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/2089/1/012071
Subject(s) - multiplier (economics) , rounding , merge (version control) , factoring , computer science , speedup , finite field , key (lock) , arithmetic , computer hardware , computer engineering , parallel computing , algorithm , mathematics , computer security , finance , economics , macroeconomics , operating system , combinatorics
In this paper, design of high speed and area efficient finite field multiplier using factoring technique for communication is implemented. Data security plays very important role in present generation. Therefore, initially inputs and key are given to S-Box. The main intent of S-Box is to substitute the input data and key. After that input data and key are merged using S-Box merge. This data will be multiplied using finite field multiplier and to improve the performance along with that mix column technique is applied. Factoring technique will increase the speed of operation. After the data performs shift row operation. At last rounding is performed to the obtained data. At last simulation results shows that effective outcome in terms of delay, memory and security.