Open AccessDesign and Implementation of AGU based FFT Pipeline Architecture
Author(s) -
Ganjikunta Ganesh Kumar,
Maturi Chandra,
Keshava Prasanna,
Mahadevappa Mahesh
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/2089/1/012070
Subject(s) - fast fourier transform , pipeline (software) , computer science , parallel computing , computation , throughput , split radix fft algorithm , rader's fft algorithm , digital signal processing , prime factor fft algorithm , computer hardware , algorithm , fourier transform , wireless , mathematics , telecommunications , fourier analysis , mathematical analysis , short time fourier transform , programming language
Present it is most needful task to get various applications with parallel computations by using a Fast Fourier Transform (FFT) and the derived outputs should be in regular format. This can be achieved by using an advanced technique called Multipath delay commutator (MDC) Pipelining FFT processor and this processor will be capable to perform the computation of a different data streams at a time. In this paper the design and implementation of AGU based Pipelined FFT architecture is done Caluclation of a butterfly is done within 2 cycles by the instructions proposed. A Data Processing Unit (DPU) is employed in this pipeline architecture and supports the instructions & an FFT Adress Generation Unit (FAGU) caluclates butterfly input & output data adresses automatically. The DPU proposed sysyem requires less area compared to commericial DSP chips. Futhermore, the proposed FAGU reduces the number of FFT computation cycles. The FFT design architecture will have real data paths. With various FFT sizes, different radix & various parallesim levels, the FFT can be mapped to the pipeline architecture. The most attractive feature of the pipelined FFT architecture is it consists of bit reversal operation so it requires little number of registers and better throughput.