Open AccessHardware Design and Implementation of Image Processing System Based on FPGA
Author(s) -
Dong Mei Zhao,
Bo Zhou,
Yang Song,
Ling Li
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/2010/1/012089
Subject(s) - computer hardware , computer science , field programmable gate array , virtex , embedded system , data transmission , interface (matter) , transmission (telecommunications) , chip , image processing , image (mathematics) , operating system , computer vision , telecommunications , bubble , maximum bubble pressure method
Discussed the hardware design and implementation of the image processing system with Virtex-XC5VSX95T as the algorithm processing chip. The large-capacity data storage chip XCF128X is selected to store the program flow. The user clock, DDR2 clock, SATA clock and other clock modules are designed. Designed LVDS and SATA as a high-speed data interface for image data transmission. Designed RS-422 as a communication interface for parameter, command and status data transmission. DDR2 memory modules and NAND Flash are as memory for image data caching. Dedicated voltage regulator chip is selected to meet the requirements of each module of the system for DC voltage. The test proves that the hardware design of the image processing system is correct and can realize the expected function.