Open AccessBridge Design between AXI Lite and AHB Bus Protocol
Author(s) -
Jaymin Patel,
Yash Shah,
L. He
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1993/1/012008
Subject(s) - bridge (graph theory) , verilog , computer science , chip , reading (process) , embedded system , computer architecture , computer hardware , telecommunications , field programmable gate array , medicine , political science , law
Architecture of bridge model between AXI Lite and AHB for this paper were simulated using Synopsys VCS and DC in Verilog HDL. Bridge structure mainly comprises of arbitration techniques, control signals, multiplexing techniques for writing data signals and Decoder for reading data section. In this work, bridge model between AHB and AXI lite was simulated and characterized. The proposed model of bridge design provides efficient communication between on chip bus protocols like AXI and AHB on chip in the era of deep sub-micron technology where channel side is reduced as much as 5 nm.