Open AccessA fast on-chip debugging design for RISC-V processor
Author(s) -
Shan Gao,
Wan’ang Xiao,
Zhenghong Yang,
Dehua Wu,
Wanlin Gao
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1976/1/012056
Subject(s) - debugging , background debug mode interface , computer science , algorithmic program debugging , reduced instruction set computing , embedded system , interface (matter) , software , chip , operating system , computer hardware , instruction set , telecommunications , bubble , maximum bubble pressure method
In order to improve the efficiency of on-chip debugging, a fast on-chip debugging design is proposed, which adopts JTAG interface and is applied in RISC-V processor. In this paper, we extend some debugging instructions, effectively reducing data entry by operating the debugging bus directly, and realize the breakpoint, pause, single step, et al., providing conveniences for the development and debugging of the software system.