Open AccessPCIE IP Validation Process Across Process Corner, Voltage and Temperature Conditions
Author(s) -
N. I. A. Karim,
Aeizaal Azman A. Wahab,
S. S. N. Alhady,
W. A. F. W. Othman,
Hazmarini Husin
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1969/1/012026
Subject(s) - pci express , debugging , field programmable gate array , computer science , robustness (evolution) , process (computing) , embedded system , initialization , physical layer , operating system , biochemistry , chemistry , programming language , wireless , gene
IP validation has become more challenging for FPGA device as it supports high operating speed. PCIe is an IP used for high-speed data transfer. The link training and Initialization takes place at physical layer to initialize the link width and link data rate. The physical layer is getting more complex when it supports higher speed. The stability of link training is improved by optimizing the soft logic design in application layer. Two protocol tests usually validated in industry are link up testing and link & higher layer testing. Debugging tools supported by Quartus are fully utilized to detect any failure during link training. The characterization of link performance covers process corners, voltage and temperature conditions are hard to analyse. The H0 statement shows a significant difference for passing and failing case. The p-value is greater than 0.05 proved H0 statement is accepted. The difference on passing and failing percentage is insignificantly impacting overall link performance of PCIe. It concludes that the bug is random and not caused by any defects on the silicon layout of FPGA device. Thus, IP validation shows the robustness of the device and able to comply with base specification of PCIe.