Open AccessVLSI Tree-Based Inference Design Applications for Low-Power Learning
Author(s) -
V. Nagaraju,
Gayathri Suresh,
C Uthayakumar,
G O Jijina
Publication year - 2021
Publication title -
journal of physics. conference series
Language(s) - English
Resource type - Journals
SCImago Journal Rank - 0.21
H-Index - 85
eISSN - 1742-6596
pISSN - 1742-6588
DOI - 10.1088/1742-6596/1964/6/062047
Subject(s) - computer science , inference , scheduling (production processes) , computer engineering , tree (set theory) , very large scale integration , field programmable gate array , architecture , real time computing , artificial intelligence , computer hardware , embedded system , mathematical analysis , mathematics , art , operations management , economics , visual arts
For the decision tree ensemble, this paper suggests a hardware architecture utilizing many feature channels. The proposed work uses the complexity of function channels for rapid identification compared to parallel processing in spatial domain scheduling to achieve conflict-free system memory. The results’ analysis demonstrates that only an FPGA implementation of the new architecture with a pedestrian sensor collated channel feature will conduct 229 thousand pulses per second at an operational value of 100 MHz while providing relatively limited resources. Checking estimation systems’ electricity-accuracy trade-offs has become central. This research evaluates the nature of data sets, investigating the outcomes of design difficulty or intensity of accuracy approximation. We improved the simulations’ precision by up to 6.7 percent by quantizing the inputs to small sizes relative to specific scenarios. The gap in model complexity was more important than source distance in terms of capacity, as we achieved reductions of up to 67 percent by reducing tree depth.